An Intermediate Representation for the Exploitation of Instruction Level Parallelism in Embedded Synthesis and VLIW Compilation Environments

This paper introduces the All-Pairs Common Slack Graph (APCSG), an intermediate representation of the instruction level parallelism that exists within a computation. The APCSG is intended for use in high level synthesis systems and compilers that target VLIW architectures. To exploit the benefits of the APCSG, we have developed the Parallel Template Generation Algorithm, a general purpose framework for compilation and synthesis optimizations. The efficacy of the framework is established by applying it to four problems at the forefront of compilation and synthesis research: (1) global resource allocation during CDFG synthesis; (2) instruction scheduling for VLIW architectures; (3) generation application-specific VLIW instruction set extensions; and (4) code compression for VLIW architectures.